Three-dimensional integrated circuits (3-D ICs) have been shown to reduce on-chip global interconnect lengths and thus alleviate delay and power consumption problems. 3-D ICs can also facilitate the integration of dissimilar technologies (digital, analog, radio-frequency circuits, et al.). In a 3-D IC, multiple active layers or substrates are vertically stacked on top of each other and are interconnected using “short” vertical links. These “short” vertical links are referred to as through-silicon vias. Despite being “short”, through-silicon vias have high aspect ratios: the radius of a through-silicon via may be in the order of several micrometers while its length is usually over 50 micrometers.
As fabrication technologies for through-silicon vias have progressed, accurate and efficient techniques for through-silicon via impedance extraction are needed for performance evaluation of circuits and systems built in 3-D ICs and for design optimization of 3-D IC interconnections. Conventional impedance extraction techniques may not be able to account for the unique location, size, and shape of through-silicon vias. For example, a significant portion of a through-silicon via is located inside the silicon substrate, increasing substrate effects significantly. The radii of through-silicon vias, in the order of several micrometers, could be comparable to the skin depth of copper even in relatively low frequencies such as hundreds of megahertz's. Some assumptions used in conventional techniques may thus become invalid. Moreover, the through-silicon via is not inside the same material, but inside a stack of layered materials. The effect of a single dipole inside the substrate cannot be written as a simple summation of dipoles inside a homogeneous space. Therefore, the z-dependence of the Green's functions cannot be easily extracted and the generation of impedance expressions is very cumbersome. In addition, through-silicon vias cannot be efficiently discretized in terms of rectangular filaments which are standard basis functions for two-dimensional impedance extraction. Accordingly, it is desirable to develop through-silicon via impedance extraction techniques that offer a good mix of speed, accuracy and generality.